In driving a liquid crystal panel of a dot-sequential active-matrix liquid crystal display device by alternating current, before a video signal is supplied to pixels via data signal lines, each of the data signal lines is precharged. With this, each of the pixels is stably charged so as to have a desired quantity of electric charge. In this case, because the total wiring capacitance of the data signal lines is high, an attempt to precharge all the data signal lines at once requires a precharge power supply having high driving capability. This problem can be solved by a technique for precharging each unit of a small number of data signal lines.
For example, Japanese Unexamined Patent Application No. 295520/1995 (Tokukaihei 7-295520; published on Nov. 10, 1995) discloses an arrangement. According to this arrangement, when a video signal is outputted to a data signal line, a switch of another data signal line is turned on with the use of a signal for sampling the video signal outputted from a shift register of a data signal line driver, so that precharge is performed by using power supplied from a precharge power supply.
According to Tokukaihei 7-295520, in order to output the video signal to the data signal lines in a dot-sequential manner, each of the data signal lines is provided with a switch, such as a MOSFET as well as a TFT, which has a capacitive control terminal (e.g., a gate), and the switch is switched between conductive and nonconductive states by controlling the charging voltage of the control terminal. The switch is switched in a dot-sequential manner by a control signal (e.g., a gate signal) that is shifted, in a horizontal direction, and outputted by a shift register generally including a plurality of flip-flops. Further, each of the data signal lines is further provided with a similar switch that is so switched between conductive and nonconductive states in a dot-sequential manner as to perform precharge.
According to the arrangement of Tokukaihei 7-295520, a circuit for performing precharge is provided in the data signal line driver. This makes it possible to reduce the amount of space that a precharge circuit occupies, e.g., to ensure that a liquid crystal display device has a sufficient amount of space for a frame.
However, according to the data signal line driver of Tokukaihei 7-295520, a signal for switching on and off a sampling switch for sampling the video signal is used also as a signal for switching on and off a precharge switch of another data signal line. This causes such a problem that display quality deteriorates, for example, due to a decrease in display uniformity.
That is, precharge to be performed by alternating current is performed so that the respective potentials of each data signal line and a pixel capacitor are so greatly changed as to be reversed in polarity with respect to those obtained when the previous video signal was sampled. Therefore, on this occasion, the switching of the switch is accompanied by a high impulse-like charging current. Since the switch has a capacitive control circuit, a relatively high frequency component of the high charging current may be transmitted to a control signal circuit of the switch via a capacitor of the control terminal, thereby oscillating the potential of the control signal circuit and further oscillating, via a control terminal of a video signal writing switch, a video signal that is to be supplied to a data signal line. Such oscillations of the video signal causes display quality to deteriorate, for example, due to a decrease in display uniformity.
In order to solve such a problem, Japanese Unexamined Patent Application No. 54235/2004 (Tokukai 2004-54235; published on Feb. 19, 2004), filed previously by the applicant of the present invention, which has already been published as a Japanese Unexamined Patent Application discloses an arrangement in which an output circuit for outputting a signal for switching on and off a sampling switch or an output circuit for outputting a signal for switching on and off a precharge circuit is used. According to this arrangement, a high current, accompanying precharge, which flows through a data signal line can be prevented from oscillating, via a capacitive control terminal of a precharge switch, the potential of a video signal that is to be written in a data signal line in which writing is currently performed.
An example of how a data signal line driver disclosed in Tokukai 2004-54235 is arranged will be described below with reference to FIGS. 30 and 31.
As shown in FIG. 30, the data signal line driver 131 includes a shift register 131a and a sampling section 131b. Moreover, the shift register 131a includes a plurality of set-reset flip-flops srff1, srff2, . . . and switch circuits asw1, asw2, . . . respectively corresponding to the set-reset flip-flops srff1, srff2, . . . .
The flip-flops srff1, srff2, srff3, . . . output output signals dq1, q1, q2, . . . , respectively. Among these output signals, the output signals q1, q2, . . . outputted by the second and subsequent flip-flops srff2, srff3, . . . are inputted to switches v_asw1, v_asw2, . . . via buffers Buf1, Buf2, . . . provided in the sampling section 131b, respectively. Each of the switches v_asw1, v_asw2, . . . of the sampling section 3B is a switch having a capacitive control terminal (e.g., a gate), and the switches v_asw1, v_asw2, . . . become conductive upon receiving the output signals q1, q2, . . . , respectively. When the switches v_asw1, v_asw2, . . . become conductive, the switches v_asw1, v_asw2, . . . output, to data signal lines sl1, sl2, . . . , the potential of an analog video signal VIDEO inputted in common to the switches v_asw1, v_asw2, . . . , respectively. That is, each of the output signals q1, q2, . . . serves as a timing pulse by which the video signal VIDEO is sampled.
Further, the output signals dq1, q1, q2, . . . are inputted as control signals to the switch circuits asw1, asw2, asw3, . . . , respectively. When the switch circuits asw1, asw2, . . . become conductive, the odd-numbered ones of the switch circuits asw1, asw2, . . . load and outputs a clock signal sck, and the even-numbered ones of the switch circuits asw1, asw2, . . . load and output a clock signal sckb. The clock signal sckb is an inversion signal of the clock signal sck.
Moreover, the switch circuits asw1, asw2, . . . output output signals dsr1, sr1, sr2, . . . , respectively. These output signals each serve as a set signal that is to be sent to the next flip-flop srff and as a reset signal that is to be sent to the previous flip-flop srff, and here serve as input signals that are to be respectively sent to switches p_asw2, p_asw3, . . . . Further, the first flip-flop srff1 receives a start pulse ssp as a set signal, and the start pulse ssp serves also as an input signal that is to be sent to a switch p_asw1.
As with the switches v_asw1, v_asw2, . . . , each of theses switches p_asw1, p_asw2, . . . of the sampling section 131 is a switch having a capacitive control terminal. The switches p_asw1, p_asw2, . . . become conductive upon receiving the start pulse ssp and the output signal dsr1, sr1, sr2, . . . , respectively. When the switches p_asw1, p_asw2, . . . become conductive, the switches p_asw1, p_asw2, . . . output, to the data signal lines sl1, sl2, . . . , a precharging potential PVID inputted in common to the switches p_asw1, p_asw2, . . . , respectively. That is, each of the start pulse ssp and the output signal dsr1, sr1, sr2, . . . serves as a control signal by which precharge is performed.
Provided so as to be orthogonal to the data signal lines sl1, sl2, . . . are scanning signal lines g11, g12, . . . . Moreover, at points of intersection between the data signal lines sl and the scanning data signal lines gl, pixels Pix1_1, Pix1_2, . . . are provided in a matrix manner, respectively.
FIG. 31 is a timing chart concerning the data signal line driver 131 arranged as described above. When the start pulse ssp is inputted, the start pulse ssp is also inputted to the switch p_asw1, so that the data signal line sl1 is precharged. On this occasion, the switch v_asw1 is nonconductive. Therefore, the precharging potential PVID and the video signal VIDEO do not collide with each other on the data signal line sl1.
Further, upon receiving the start pulse ssp, the flip-flop srff1 outputs the output signal dq1. Upon receiving the output signal dq1, the switching circuit asw1 becomes conductive, loads the clock signal sck, and outputs the output signal dsr1. The output signal dsr1 serves as a set signal. The set signal is inputted to the flip-flop srff2, so that the flip-flop srff2 outputs the output signal q1.
Upon receiving the output signal q1, the switch asw2 becomes conductive, loads the clock signal sckb, and outputs the output signal sr1. Further, the output signal q1 serves as a timing pulse. The timing pulse is inputted to the switch v_asw1 via the buffer Buf1, so that the switch v_asw1 becomes conductive. With this, the data signal line sl1 is supplied with the video signal VIDEO. On this occasion, the start pulse ssp has already become low, so that the switch p_asw1 is nonconductive. Therefore, the precharging potential PVID and the video signal VIDEO do not collide with each other on the data signal line sl1.
Further, since the output signal dsr1 causes the switch p_asw2 to be conductive, the data signal line sl2 is precharged at the same time as the video signal VIDEO is outputted to the data signal line sl1.
Thus, sampling is performed in a dot-sequential manner by sequentially repeating an operation of supplying the video signal VIDEO to a data signal line sln after the data signal line sln has been precharged and precharging a data signal line sl(n+1) while supplying the video signal VIDEO to the data signal line sln.
Further, Japanese Unexamined Patent Application No. 218738/1999 (Tokukaihei 11-218738; published on Aug. 10, 1999) describes a technique for writing a precharge signal in data lines in a line-sequential manner in an electro-optic device, including a bidirectional shift register, which carries out a reversing display. According to the technique described in this document, an output stage located two stages before an output stage for outputting a sampling circuit driving signal outputs a precharge circuit driving signal, and a precharge signal switching circuit selects, in accordance with the shift direction of the bidirectional shift register, an output stage for outputting a precharge circuit driving signal.
Note that Japanese Unexamined Patent Application No. 135093/2001 (Tokukai 2001-135093; published on May 18, 2001), filed previously by the applicant of the present invention, which has already been published as a Japanese Unexamined Patent Application discloses an arrangement in which a switch circuit loads a clock signal in response to an output sent from a set-reset flip-flop constituting each stage of a shift register and in which the clock signal serves as a set signal that is to be sent to the next set-reset flip-flop. Further, Japanese Unexamined Patent Application No. 307495/2001 (Tokukai 2001-307495; published on Nov. 2, 2001) and Japanese Unexamined Patent Application No. 339985/2000 (Tokukai 2000-339985; published on Dec. 8, 2000), filed previously by the applicant of the present invention, which have already been published as a Japanese Unexamined Patent Application disclose an arrangement in which a clock signal is loaded in response to an output sent from a set-reset flip-flop constituting each stage of a shift register and in which the clock signal is level-shifted so as to serve as a set signal that is to be sent to the next set-reset flip-flop.
However, according to the respective techniques of Tokukaihei 7-295520 and Tokukai 2004-54235, before a video signal is outputted to a data signal line, precharge is performed by using a signal outputted by an output stage located right in front of an output stage for outputting the video signal to the data signal line.
This makes it necessary to add a precharge output stage (dummy stage, dummy circuit) right in front of the shift register in order to precharge a first data signal line or first and second data signal lines, thereby increasing the amount of space that the driving circuit occupies. For example, according to the arrangement in which an output stage is precharged by using an output stage located two stages before the output stage, it is necessary to provide two dummy stages.
Furthermore, in addition to the increase in the amount of space that a dummy stage occupies, there is an increase in the amount of space in which wires are provided. This causes an increase in the amount of space for a frame surrounding a display area. Therefore, the respective techniques of Tokukaihei 7-295520 and Tokukai 2004-54235 are not suitable for a display device, such as a display device to be provided in a portable phone or the like, which is required to be small and to have, for the purpose of miniaturization, a small amount of space for a frame surrounding a display area.
Further, according to the technique of Tokukaihei 11-218738, it is necessary to provide a precharge signal switching circuit for selecting, in accordance with the shift direction of a bidirectional shift register, an output stage for outputting a precharge circuit driving signal. The precharge signal switching circuit receives a precharge circuit driving signal sent from an output stage located two stages before the precharge signal switching circuit along each shift direction, and receives a precharge circuit driving signal sent from an output stage located two stages after the precharge signal switching circuit along each shift direction. This causes an increase in the amount of space that the precharge signal switching circuit occupies and an increase in the amount of space in which wires are provided, thereby causing an increase in the size of the driving circuit.
Thus, the conventional display device driving circuit has such a problem that the amount of space that the driving circuit occupies and the amount of space in which wires are provided are increased for the purpose of performing precharge. Note that none of Tokukai 2001-135093, Tokukai 2001-307495, and Tokukai 2000-339985 discloses or suggests anything about precharge.